✦ Talk 1: Harnessing Agentic AI for Chip Design: A New Era of Design Excellence
Dr. Chuck Alpert, Cadence AI Fellow
Dr. Charles (Chuck) Alpert received a B.S. in Math and Computational Sciences and a B.A. degree in History from Stanford in 1991, and a Ph.D. in Computer Science in 1996 from UCLA. He then worked for IBM research, focusing on physical design research in placement, buffering, routing and wire synthesis. In 2014, Chuck joined Cadence Design Systems, where he has worked in many parts of the digital implementation portfolio, managing several teams and projects including logic synthesis, clock tree synthesis, global routing, and most recently running Cerebrus, Cadence’s AI-based Digital Exploration product.
Chuck is an IEEE Fellow and published over 100 papers in leading conferences and journals in electronic design automation. He has received over 100 patents and is a Cadence Master Inventor. He has also co-edited the Handbook on Physical Design Automation, and has served as deputy editor-in-chief for IEEE Transactions on Computer-Aided Design. He has also served as general chair for the 2016 IEEE/ACM Design Automation Conference, the Tau and CANDE Workshops, and the ACM International Symposium on Physical Design.
✦ Talk 2: Future of Simulation Driven Product Innovation for Devices, Circuits and Systems
Abstract. Traditionally, devices, circuits and systems are designed with electronic design automation tools, and simulated and validated for correctness with computer aided engineering tools. In the past, simulation tools were used to model specific, solitary physics such as mechanical structures, fluid dynamics, or electromagnetic interactions by solving second order partial differential equations using numerical methods. Today, simulation tools solve multi-physics problems (fluid-structure-electromagnetics interactions) at scale using the most complex solvers. This talk will discuss five key pillars of the Ansys long term technology strategy: (1) Core Physics and Numerical Methods including novel solver methods, geometry and meshing, and multi-domain multiscale simulation; (2) High-Performance Computing using shared memory, message-passing, GPUs and quantum computing; (3) AI/Machine learning for solver acceleration and automatic solver settings; (4) Cloud and Platforms for cloud marketplace and cloud native SAAS; (5) Digital Engineering including MBSE and digital twins.
Dr. Prith Banerjee, Chief Technology Officer, Ansys
Prith Banerjee is Chief Technology Officer at ANSYS, a leader in engineering simulation. Prior to that, he was CTO of Schneider Electric, CTO of ABB, Managing Director of R&D at Accenture, and Director of HP Labs. Previously he spent 20 years in academia as Professor, Chairman and Dean at the University of Illinois and Northwestern University. He has founded two companies, AccelChip and Binachip. He has served on the Board of Cray, CUBIC. Turntide, and Anita Borg Institute, and the Technical Advisory Boards of Ambit, Atrenta, Calypto, Cypress, Ingram Micro, Virsec, and Ampere.
He is a Fellow of the AAAS, ACM and IEEE. He is the author of more than 350 papers and a book entitled INNOVATION FACTORY. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.
✦ Talk 3: Transforming EDA with Foundational Models: From Autonomous Design Agents to Post-training Customization
Abstract: In this talk, we present a review of how foundational models are transforming electronic design automation (EDA) across the entire design stack: from system-level architecture to RTL generation, logic synthesis, physical implementation and design for manufacturing. Drawing on insights from recent research contributions, we examine three dominant methodological trends: autonomous agent frameworks, domain adaptation via fine-tuning and specialized tokenization, and application-specific customization. We will highlight how multi-modal representations, which blend textual, graph-based, and visual circuit data, are enabling unprecedented design capabilities, with domain-adapted models consistently outperforming general-purpose counterparts. We hope our talk could offer a forward-looking perspective at the post-training era of foundational models (LLMs and diffusion models) in EDA and provides practical guidance for researchers and practitioners aiming to leverage these technologies for next-generation chip designs.
Prof. Yiran Chen, John Cocke Distinguished Professor, Duke University
Dr. Yiran Chen earned his B.S. in 1998 and M.S. in 2001 from Tsinghua University and completed his Ph.D. in 2005 at Purdue University. In 2010, he joined the University of Pittsburgh as an Assistant Professor, where he was later promoted to Associate Professor with tenure in 2014, holding the prestigious Bicentennial Alumni Faculty Fellowship. He currently serves as the John Cocke Distinguished Professor of Electrical and Computer Engineering at Duke University.
Dr. Chen has published one book and more than 350 technical publications and has been granted 93 US patents. He serves or served the associate editor of several IEEE and ACM transactions/journals and served on the technical and organization committees of more than 50 international conferences. He received 6 best paper awards and 12 best paper nominations from international conferences. He is the recipient of NSF CAREER award and ACM SIGDA outstanding new faculty award. He is a Fellow of the IEEE and Distinguished Member of ACM, a distinguished lecturer of IEEE CEDA, and the recipient of the Humboldt Research Fellowship for Experienced Researchers.