The PDF version of the full program is available here.
✪ Indicates best paper candidates
Welcome reception at Courtyard Terrace; main conference at Santa Cruz; breakfast/lunch/dinner at Sunset Restaurant.
✦ Sunday, Sept. 7, 2025
| 18:30 – 21:00 | Welcome Reception @ Courtyard Terrace |
✦ Monday, Sept. 8, 2025
| 07:30 – 08:30 | Breakfast @ Sunset Restaurant |
| 08:30 – 08:45 | Opening Remarks |
| 08:45 – 09:30 | Keynote 1: Harnessing Agentic AI for Chip Design: A New Era of Design Excellence Chuck Alpert (Cadence AI Fellow) |
| 09:30 – 09:40 | Short Break |
| 09:40 – 10:40 | Session 1: LLM-Guided RTL Generation and Optimization Moderator: Paul Franzon (NC Statue University) |
| ASPEN: LLM-Guided E-Graph Rewriting for RTL Datapath Optimization Niansong Zhang, Chenhui Deng, Johannes Maximilian Kuehn, Chia-Tung Ho, Cunxi Yu, Zhiru Zhang, Haoxing Ren | |
| TuRTLe: A Unified Evaluation of LLMs for RTL Generation Dario Garcia-Gasulla, Gokcen Kestor, Emanuele Parisi, Miquel Alberti-Binimelis, Christian Gutierrez, Razine Moundir Ghorab, Orlando Montenegro, Bernat Homs, Miquel Moreto | |
| Verilog Code Generation of Hierarchical Design Using LLMs (Short Paper) Geuna Chang, Shilong Zhang, Seohyun Kim, Woojin Kim, Youngsoo Shin | |
| RTLExplain: A Structured Approach to RTL Code Summarization and Question Answering for Medium-to-Large Designs Using LLMs (Short Paper) Ting-Hsun Chi, Charles Mackin, Luyao Shi, Prashanth Vijayaraghavan, Hsinyu Tsai, Ehsan Degan | |
| 10:40 – 11:00 | Coffee Break |
| 11:00 – 12:30 | Session 2: Hardware Design and Verification (1) Moderator: Caiwen Ding (University of Minnesota) |
| Firefly: Shedding Light on Verification Gaps Using LLM-Powered Mutation Testing Bekzat Skakov, Sanzhar Abduraimov, Olzhas Nurman, Nursultan Kabylkas | |
| LLM-assisted Path Exploration for RTL Verification ✪ Yan Tan, Yangdi Lyu, Xiangchen Meng | |
| VCDiag: Classifying Erroneous Waveforms for Failure Triage Acceleration Minh Luu, Surya Jasper, Khoi Le, Evan Pan, Michael Quinn, Aakash Tyagi, Jiang Hu | |
| Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA Weihua Xiao, Derek Ekberg, Siddharth Garg, Ramesh Karri | |
| BugGen: A Self-Correcting Multi-Agent LLM Pipeline for Realistic RTL Bug Synthesis (Short Paper) Surya Jasper, Minh Luu, Evan Pan, Aakash Tyagi, Michael Quinn, Jiang Hu, David Kebo Houngninou | |
| 12:30 – 1:30 | Lunch @ Sunset Restaurant |
| 13:30-15:00 | Session 3: LLMs for Hardware Description and Optimization Moderator: Ismail Bustany (AMD) |
| ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accelerate RTL Code Generation Chenhui Deng, Yun-Da Tsai, Guan-Ting Liu, Zhongzhi Yu, Haoxing Ren | |
| hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation Charles Hong, Brendan Roberts, Huijae An, Alex Um, Advay Ratan, Sophia Shao | |
| Schemato: An LLM for Netlist-to-Schematic Conversion Chia-Yu Hsieh, Ali Momeni, Lukas Mauch, Augusto Capone, Eisaku Ohbuchi, Lorenzo Servadei | |
| Context-Enhanced Architectural Specification Generation for SoC Designs Md Rubel Ahmed, Sadiba Nusrat Nur, Rickard Ewetz | |
| LLM-VeriPPA: Power, Performance, and Area Optimization aware Verilog Code Generation with Large Language Models (Short Paper) Kiran Thorat, Jiahui Zhao, Yaotian Liu, Amit Hasan, Hongwu Peng, Xi Xie, Bin Lei, Caiwen Ding | |
| 15:00 – 15:20 | Coffee Break |
| 15:20 – 16:20 | Special session Moderator: Vishal Khandelwal (Synopsys) |
| AI-Driven Design Automation for Multi-Chip Integration in AI Chips Sung Kyu Lim (University of Southern California) | |
| Scalable Physical Design Optimization with GPU Acceleration and Generative AI Mark Ren (Nvidia) | |
| Transforming Design and Verification with Generative AI Ramesh Narayanaswamy (Synopsys) | |
| 16:20 – 16:30 | Short Break |
| 16:30 – 17:40 | Session 4: Design Flow Optimization Moderator: Ulf Schlichtmann (Technical University of Munich) |
| Optimizing CUDA Graph Scheduling with Reinforcement Learning: A Case Study in SSTA Propogation Cheng-Hsiang Chiu, Chedi Morchdi, Chih-Chun Chang, Cunxi Yu, Yi Zhou, Tsung-Wei Huang | |
| NeuroSim Agent: Automated Compute-in-Memory Accelerator Deployment with Transferable Reinforcement Learning and Dynamic Design Space Pruning Ming-Yen Lee, Shimeng Yu | |
| BeyondPPA: Human-Inspired Reinforcement Learning for Post-Route Reliability Aware Macro Placement ✪ Ishraq Tashdid, Valentina Terry, Jordan Merkel, Tasnuva Farhee, Sazadur Rahman | |
| Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper (Short Paper) Cunxi Yu | |
| 18:00 – 19:30 | Dinner and Networking @ Sunset Restaurant |
✦ Tuesday, Sept. 9, 2025
| 07:30 – 08:30 | Breakfast @ Sunset Restaurant |
| 08:30 – 09:15 | Keynote 2: Future of Simulation Driven Product Innovation for Devices, Circuits and Systems Prith Banerjee (ANSYS CTO) |
| 09:15 – 09:25 | Short Break |
| 09:25 – 10:25 | Panel: The Autonomous Future of IC Design: Fast, Scalable, and 99% Correct Panelists: Chuck Alpert (Cadence), Pierre-Emmanuel Gaillardon (PrimisAI), Hamid Shojaei (ChipStack), Ramesh Narayanaswamy (Synopsys) Moderator: Igor Markov (Synopsys) |
| 10:25 – 10:45 | Coffee Break |
| 10:45 – 12:15 | Session 5: Hardware Design and Verification (2) Moderator: Marilyn Wolf (University of Nebraska-Lincoln) |
| SALAD: Systematic Assessment of Machine Unlearning for LLM-aided Hardware Design Zeng Wang, Minghao Shao, Rupesh Raj Karn, Lakshmi Likhitha Mankali, Jitendra Bhandari, Ramesh Karri, Ozgur Sinanoglu, Muhammad Shafique, Johann Knechtel | |
| Machine Learning Driven Early Clustering for Multi-bit Flip-Flop Allocation Jooyeon Jeong, Taewhan Kim | |
| Recurrent CircuitSAT Sampling for Sequential Circuits Arash Ardakani, Kevin He, John Wawrzynek | |
| ORFS-agent: Tool-Using Agents for Chip Design Optimization ✪ Amur Ghose, Andrew Kahng, Sayak Kundu, Zhiang Wang | |
| A Hybrid Optimization Framework for Power-Efficient Pulsed Latch Utilization in Clock Networks (Short Paper) Yuntao Lu, Dehua Liang, Siting Liu, Yuhao Ji, Yu Zhang, Xuanqi Chen, Xia Lin, Jinlei Lu, Weihua Sheng, Bei Yu | |
| 12:15 – 13:15 | Lunch @ Sunset Restaurant |
| 13:15 – 14:55 | Session 6: Physical Design Automation Moderator: Rhett Davis (NC State University) |
| On-Chip Decoupling Capacitor Placement with Impedance Constraint for DRAM Design Minseung Shin, Shilong Zhang, Geuna Chang, Youngsoo Shin | |
| Dr. Guide: AI-Guided Detailed Routing Qijing Wang, Wing Ho Lau, Tsung-Yi Ho, Evangeline F.Y. Young, Martin D.F. Wong | |
| Machine-Learning Driven Cell Library Compaction Handong Cho, Taewhan Kim | |
| Recursive Learning-Based Virtual Buffering for Analytical Global Placement Andrew Kahng, Yiting Liu, Zhiang Wang | |
| PROMPT: Prediction Model for RRAM Programming Optimized by Adaptive Mechanism and Progressive Continuous Transformation (Short Paper) Yanxing Guo, Ling Liang, Zihao Zheng, Zezhi Cheng, Yuhang Yang, Linbo Shan, Zongwei Wang, Yimao Cai | |
| EDA Tool Parameter Optimization through Fast and Reliable Machine-Learning based Rank Prediction Model (Short Paper) Doyeon Won, Taewhan Kim | |
| 14:55 – 15:15 | Coffee Break |
| 15:15 – 16:15 | Industry Session Moderator: Vishal Khandelwal (Synopsys) |
| MAMBO: ML Accelerated Multi-Agent Black-Box Optimization for Enhancing Standard Cell Synthesis Quality Tianchi Liu, Sriram Madhavan, Dastagiri Dudekula, Luke Thomas, Ivo van Zandvoort, Maarten Berkens (Applied Materials) | |
| Trajectory.AI: An Automated P&R Flow Trajectory Agent Wei Zeng, Sudipto Kundu, Jerry Wu (Synopsys) | |
| Optimal Input Vector Generation for Transistor-level Power Analysis Using Machine Learning Anurag Umbarkar, Nugu Dhanwada, Kartik Acharya, Yisen Wang, Abraham Mathews (IBM) | |
| 16:15 – 16:25 | Short Break |
| 16:25 – 17:35 | Session 7: Secure Hardware Design using LLMs Moderator: Niansong Zhang (Cornell University) |
| HADA: Leveraging Multi-Source Data to Train Large Language Models for Hardware Security Assertion Generation Weimin Fu, Yiting Wang, Zelin Lu, Xiaolong Guo, Gang Qu | |
| LASSO: LLM-Aided Security Property Generation for Assertion-based SoC Verification ✪ Dinesh Reddy Ankireddy, Sudipta Paria, Aritra Dasgupta, Sandip Ray, Swarup Bhunia | |
| Trusting the Machine: How Secure is LLM-Generated RTL Code? Zahin Ibnat, Paul E. Calzada, Dipayan Saha, Hasan AI-Shaikh, Sujan Kumar Saha, Jingbo Zhou, Farimah Farahmandi, Mark Tehranipoor | |
| ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis (Short Paper) Suresh Purini, Siddhant Garg, Mudit Gaur, Sankalp Bhat, Sohan Mupparapu, Arun Ravindran | |
| 18:00 – 19:30 | Dinner @ Sunset Restaurant |
✦ Wednesday, Sept. 10, 2025
| 07:30 – 08:30 | Breakfast @ Sunset Restaurant |
| 8:30 – 8:35 | Award Ceremony |
| 08:35 – 09:20 | Keynote 3: Transforming EDA with Foundational Models: From Autonomous Design Agents to Post-training Customization Yiran Chen (Duke University) |
| 09:20 – 09:30 | Short Break |
| 09:30 – 10:30 | Session 8: Hardware Design and Verification (3) Moderator: Akhilesh Kumar (Ansys) |
| Privacy-Preserving Data and Model Sharing for EDA via Inference Control and DP-SGD Ziyu Deng, Rada Chirkova, Leigh Anne Clevenger, William Rhett Davis | |
| Prompting for Power: Benchmarking Large Language Models for Low-Power RTL Design Generation Kevin Immanuel Gubbi, Marcus Halm, Sarbani Kumar, Arvind Sudarshan, Pavan Dheeraj Kota, Mohammadnavid Tarighat, Avesta Sasan, Houman Homayoun | |
| ML-Enhanced Performance and Power Estimation for DNNs on Heterogenous SoCs (Short Paper) Surya Selvam, Jacob R. Stevens, Sujit Dey, Anand Raghunathan | |
| Improving Last-Mile Coverage in Functional Verification (Short Paper) Chengjia Liu, Jnana Preeti Parlapalli, David Kebo Houngninou, Michael Quinn, Aakash Tyagi, Jiang Hu | |
| 10:30 – 11:00 | Coffee Break |
| 11:00 – 12:30 | Contest and Special Session Moderator: Vidya Chhabria (Arizona State University) |
| Accelerating Defect Spectroscopy with Machine Learning Models Luke Thomas, Nicola Giuliani, Enrico Piccinini, Riccardo Foiera, Sriram Madhavan (Applied Materials) | |
| Without Chip Foundational Models, AI-Native EDA for SoC Will Fail or Not? Ilhami Torunoglu (Siemens EDA) | |
| LLMs in Production With Chip Teams: Opportunities, Challenges, and Lessons Learned Kartik Hegde (ChipStack) | |
| MLCAD 2025 Contest on ReSynthAI: Physical-Aware Logic Resynthesis for Timing Optimization Using AI Vidya Chhabria | |
| 12:30 – 13:30 | Lunch @ Sunset Restaurant |
| 13:30 – 15:00 | Session 9: Analog- and Digital-Circuit Design Moderator: Cunxi Yu (University of Maryland) |
| ML-Inspired Logic Synthesis: Improving Multiplier Circuits Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca Amaru | |
| GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification Phuoc Pham, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Stefan Uhlich, Markus Leibl, Simon Hofmann, Eisaku Ohbuchi, Lorenzo Servadei, Ulf Schlichtmann, Robert Wille | |
| LASANA: Large-scale Surrogate Modeling for Analog Neuromorphic Architecture Exploration Jason Ho, James A. Boyle, Linshen Liu, Andreas Gerstlauer | |
| HR²: A PVT Aware Hierarchical RL Based Sizing Framework for Robust Analog Circuit Design Jaeheon Jung, Dongwoo Lew, JangSeok Yu, Jongsun Park | |
| Netlistify: Transforming Circuit Schematics into Netlists with Deep Learning (Short Paper) Chun-Yen Huang, Hsuan-I Chen, Hao-Wen Ho, Pei-Hsin Kang, Mark Po-Hung Lin, Wen-Hao Liu, Haoxing Ren | |
| 15:00 – 15:30 | Coffee Break |
| 15:30-17:00 | Session 10: Timing- and Thermal-Prediction Moderator: Yibo Lin (Peking University) |
| Priority-Aware Routing Optimization with Full-Path Delay Prediction using Machine Learning Hyunmin Jo, Heechun Park | |
| Post-Routing Path Statistical Delay Estimation Based on SGAT-GRU Prediction Framework Jingjing Guo, Xuejie Ning, Suohang Yang, Jun Yang, Zhikuang Cai | |
| Pieceformer: Similarity-Driven Knowledge Transfer via Scalable Graph Transformer in VLSI Hang Yang, Yong Liu, Yusheng Hu, Cong Hao | |
| Fast Chip Transient Temperature Simulation via Machine Learning Mohammadamin Hajikhodaverdian, Sherief Reda, Ayse Coskun | |
| Multimodal Learning-Based Thermal Solver for 3DICs with Arbitrary Chip Dimensions and Power Distributions (Short Paper) Zelin Lu, Akhilesh Kumar, Norman Chang, Haiyang He, Lang Lin, Wenbo Xia, Jie Yang, Gang Qu | |
| 17:00 – 17:10 | Closing Remarks |
| 18:00 – 19:30 | Dinner @ Sunset Restaurant |