Keynote Speakers
✦ Talk 1: The Silicon Compiler’s Second Coming: How AI will change Chip Design
Abstract. Despite the name of this conference, AI is coming for chip design only selectively. Across the EDA flow, learning wins decisively for some tasks but loses, by many orders of magnitude in speed, to conventional graph-based algorithms for others. Most of the EDA flow is, and will remain, graph-based. The dividing line is not task difficulty but how well a task’s specification ‘compresses’. Exact, provable tasks such as DRC, LVS, and equivalence checking exclude learning by construction, and graph-based algorithms remain many, many orders of magnitude faster. The sweet spot where AI genuinely inverts the cost is the prediction layer: learned surrogates for congestion, IR drop, and lithographic hotspots that run inside the optimization loop.
A single logic die now integrates on the order of 2×10¹¹ transistors, exceeding the neuron count of the human brain. The systems built from these devices increasingly match human judgment and intelligence. That milestone sharpens a question as old as the EDA field: what does automation do to the people it automates? The fear is not new. It was already present at the first Design Automation Conference in 1964, and it proved largely unfounded: unemployment today is no higher than it was 60 years ago. Automation reshaped the work without eliminating the workforce.
With AI the argument for concern is more specific. The push-button chip was the silicon-compiler dream of the 1980s, and it failed for one reason: Moore’s law widened design complexity faster than EDA synthesis could absorb it. Hand-tuned design kept winning on quality of results. That ratio is now inverting. Agentic AI may improve faster than the substrate it designs for, closing the productivity gap that once protected the human designer. The historical escape valve, that automation was always a generation behind the silicon, is closing with it. Push-button silicon compilation seems increasinly feasible. The risk is skill misalignment: capability moving faster than the workforce can retrain for new tasks. We will identify which roles compress first (predictive and exploratory) and which resist longest (specification, verification, sign-off), and ask whether the EDA community shapes that transition or is shaped by it.
Dr. Patrick Groeneveld, Senior Fellow at AMD
 | Dr. Patrick is Senior Fellow at AMD and adjunct lecturer in Stanford University’s Department of Electrical Engineering. With an extensive career in Electronic Design Automation, he has held roles at both Cadence and Synopsys and served as Chief Technologist at Magma Design Automation, where he contributed to the development of a pioneering RTL-to-GDS2 synthesis tool. Patrick has also worked with AI hardware startups and held a Full Professorship in Electrical Engineering at Eindhoven University. |
He is the Finance Chair on the Executive Committee of the Design Automation Conference. Patrick earned his MSc and PhD degrees from Delft University of Technology in the Netherlands.
✦ Talk 2: AI-Driven Paradigm Shift in Semiconductor Design & Verification: Challenges and Opportunities
Abstract. Following the transformative impact of Large Language Models (LLMs) on the software industry, the paradigm of semiconductor Design and Verification (D&V) is currently undergoing a complete restructuring. Given the hardware industry’s critical requirement for absolute security and integrity, the integration of AI has evolved from an optional enhancement into a strategic necessity, presenting challenges that differ significantly from those encountered in software development. This session provides practical insights derived from overseeing design methodologies and extensive verification for a wide range of products, spanning from Mobile APs to PMICs. I will highlight the possibilities for disruptive innovation that transcends basic automation to overcome the limitations of domain-specific expertise. Furthermore, I will address the practical hurdles we face, including the risk of ‘hallucinations’ and the inherent structural dilemmas within the EDA ecosystem. By outlining the optimal synergy between AI and EDA to maximize PPA and reduce TAT, I aim to explore the profound transformation and the accompanying paradoxes that AI will introduce to the future of semiconductor development.
Dr. Young-sik Kim, VP at Samsung
 | Dr. Young-sik Kim currently leads the Design Technology (DT) team within the System LSI Business at Samsung Electronics, where he oversees the establishment of design methodologies and the execution of large-scale verification for the entire business unit. Since joining Samsung Electronics in 2008, he has accumulated deep expertise across the entire spectrum of semiconductor design and verification through his experience in various teams. As the head of the DT team, he leads the development of design and verification methodologies for a diverse range of product lines, including Mobile AP/CP, Automotive, and Sensors, as well as PI&PD and ESD Sign-off methodologies. |
He leads extensive functional verification execution team spanning from IP to Full-Chip and Chip-2-Chip, as well as the establishment of emulator-based software pre-development platforms and performance verification. Recently, he has been focusing on research to integrate Large Language Models (LLM) and Multimodal AI technologies into semiconductor design and verification workflows, driving innovation in the next-generation semiconductor development paradigm.
✦ Talk 3: Automating Chip Design with Agentic AI Technology – From Chatbots to Long Running Agents
Abstract. Artificial Intelligence is an avenue to innovation that is touching every industry worldwide. AI has made rapid advances in areas like speech and image recognition, gaming, and even self-driving cars. In the area of chip design, we see a growing gap in what designer’s want to achieve and what the available resources and time allow. This presentation will provide an overview of recent AI trends, show how the latest AI technology including Generative and Agentic AI can be applied to optimize and automate chip design tasks from architectural design to digital and analog implementation, optimizing silicon life cycles and improving yield.
Dr. Thomas Andersen, VP at Synopsys
 | Dr. Andersen heads the artificial intelligence and machine learning design group at Synopsys, where he focuses on developing new technologies in the AI space to automate the future of chip design. He has more than 20 years of experience in the semiconductor and EDA industry. Dr. Andersen started his career at IBM’s TJ Watson Research Center in Yorktown Heights, New York, followed by managing digital implementation R&D at Magma Design Automation and Synopsys. He holds a Master’s degree from the University of Stuttgart and a Ph.D. in Computer Engineering from the University of Kaiserslautern in Germany. |
Program
✦ Saturday, September 6, 2026
| 18:30 – 21:00 | Welcome Reception |
✦ Monday, September 7, 2026 — Day 1
| 07:30 – 08:30 | Breakfast @ Sunset Restaurant |
| 08:30 – 08:45 | Opening Remarks |
| 08:45 – 09:30 | Keynote 1: The Silicon Compiler’s Second Coming: How AI will change Chip Design Patrick Groeneveld (Senior Fellow at AMD) |
| 09:30 – 09:40 | Short Break |
| 09:40 – 11:00 | Session 1: LLM-Guided RTL Generation and Optimization |
| ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation Yan Tan, Du Jiping, Xiangchen Meng and Yangdi Lyu | |
| DREAM: Design-flow and RTL Enhancement via End-to-End LLM-Assisted Method Runzhi Wang, Donghao Fang, Guanglei Zhou, Fenghua Wu, Yiran Chen and Jiang Hu | |
| VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation Yijun Shen, Minghao Shao, Yichen Zhao, Zhuoyan Yu, Boyuan Chen, Yik-Cheung Tam and Muhammad Shafique | |
| STITCH: Semantic Toolchain Integration for LLM-Driven RTL Circuit and Hardware Design Generation Karthikeya Patana, Yashwant Rajesh, Aathira Sunil, Durga Saranyu, Sri Parameswaran, Kamesh Chandrasekar, Paresh Saxena and Soumya Joshi | |
| 11:00 – 11:20 | Coffee Break |
| 11:20 – 12:40 | Session 2: RTL Verification & Assertion Generation |
| RTLInsight: Self-Evolving Debugging Skills for Online RTL Bug Root-Cause Analysis and Repair Yunsheng Bai, Ghaith Bany Hamad, Cunxi Yu, Chenhui Deng, Nathaniel Pinckney, Chia-Tung Ho, Danny Liu, Hima Swetha N and Brucek Khailany | |
| Coverage-Driven RTL Assertion Generation with Formal Exploration and Neuro-Symbolic Refinement Zhiyuan Yan, Ziyue Zheng and Hongce Zhang | |
| IntentGraph: Automated RTL Specification Completeness Analysis via Intent-Aware Formal Verification Changyuan Yu | |
| Spec2Assertion: Automatic Pre-RTL Assertion Generation by LLMs with Progressive Regularization Fenghua Wu, Runzhi Wang, Evan Pan, Aakash Tyagi, Michael Quinn, David Houngninou, Jeyavijayan Rajendran and Jiang Hu | |
| 12:40 – 13:40 | Lunch |
| 13:40 – 15:00 | Special Session 1: Open-PDKs (4 talks) |
| PKP: A Predictive Open PDK in the Era of GAA and Backside Interconnect Guoyao Cheng, Baokang Peng, Sihao Chen, Jie Lin, Runsheng Wang, Lining Zhang (Peking University) | |
| GT2N: An Open-Source 2nm Nanosheet PDK for ML Hardware Design and CAD Research Dongwon Jang, Sungwoo Jung, Sai Pranav Gooty, Md Mizanur Rahaman Nayan, Piyush Kumar, Md Nahid Haque Shazon, Sabareesh Jeevan Ram, Azad Naeemi (Georgia Institute of Technology) | |
| Nonvolatile In-Memory-Computing Neuromorphic Accelerators based on Heterogeneous Integration for Edge Smart Sensor Systems Yitao Ma (Zhejiang University) | |
| IHP 130nm PDK Krzysztof Herman (IHP Microelectronics) | |
| 15:00 – 15:20 | Coffee Break |
| 15:20 – 16:40 | Session 3: Hardware Verification & Security |
| Understanding Inference-Time Token Allocation and Coverage Limits in Agentic Hardware Verification Vihaan Patel, Vidya Chhabria and Aman Arora | |
| NoTB: Oracle-Free Triage of LLM-Generated RTL via Cross-Model Formal Consensus Elisavet Lydia Alvanaki, Jenna Yang, Biruk Seyoum and Luca Carloni | |
| CovR: Coverage-Aware Hardware Verification via Reasoning-Guided Reinforcement Learning Manar Abdelatty, Maryam Nouh and Sherief Reda | |
| TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion Saideep Sreekumar, Zeng Wang, Akashdeep Saha, Weihua Xiao, Minghao Shao, Muhammad Shafique, Ozgur Sinanoglu, Ramesh Karri and Johann Knechtel | |
| 16:40 – 16:50 | Short Break |
| 16:50 – 18:10 | Session 4: LLM Agents for EDA Flows |
| SoC-Agent: A Multi-Agent Automated System-on-Chip Development Framework with Harness Engineering Pei-Huan Tsai, Kuan-Lin Chiu, William Baisi, Pin-Yu Chen and Luca Carloni | |
| Trace2Skill: Verifier-Guided Skill Evolution for Long-Context EDA Agents Zijian Du and Nathaniel Pinckney | |
| Retrieve, Schedule, Reflect: LLM Agents for Chip QoR Optimization Yikang Ouyang, Yang Luo, Dongsheng Zuo and Yuzhe Ma | |
| EDAFLOWQA: Dual-Validated Q-Tree for a Multi-Stage EDA Log Reasoning Benchmark Chia-Tung Ho, Rongjian Liang, Cunxi Yu and Brucek Khailany | |
| 18:30 – 20:00 | Dinner |
✦ Tuesday, September 8, 2026 — Day 2
| 07:30 – 08:30 | Breakfast |
| 08:30 – 09:15 | Keynote 2: AI-Driven Paradigm Shift in Semiconductor Design & Verification: Challenges and Opportunities Young-sik Kim (VP at Samsung) |
| 09:15 – 09:25 | Short Break |
| 09:25 – 10:45 | Session 5: Placement & Routing |
| T-RADPlace: Reward-Aligned Diffusion Models for Timing-Aware Macro Placement Zhili Xiong, Haoyu Yang, Anthony Agnesina, Brucek Khailany and David Z. Pan | |
| Legalization-Aware Projected Gradient Descent for DRV Resolution at Placement Suwan Kim and Taewhan Kim | |
| Segment-Level Rerouting with Reinforcement Learning for Routing Congestion Mitigation Gyumin Kim and Heechun Park | |
| Prediction-Guided Placement Refinement for Cross-Tier Routability in Monolithic 3D ICs Gyumin Kim and Heechun Park | |
| A Hybrid Optimization Framework for Power-Efficient Pulsed Latch Utilization in Clock Networks (Short Paper) Yuntao Lu, Dehua Liang, Siting Liu, Yuhao Ji, Yu Zhang, Xuanqi Chen, Xia Lin, Jinlei Lu, Weihua Sheng, Bei Yu | |
| 10:45 – 11:05 | Coffee Break |
| 11:05 – 12:25 | Special Session 2: Agentic EDA in Industry (4 talks) |
| Academic and Industrial Experiences for Agentic Chip Design Jose Renau (Nvidia and UC Santa Cruz) | |
| Agentic AI in RTL-to-GDSII: A Perspective from the Industry Siddhartha Nath (Google DeepMind) | |
| Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows Jinyuan Deng, Zhengrui Chen, Xufeng Wei, Tianyu Xing, Chenyi Wen, Qi Sun, Cheng Zhuo (Zhejiang University) | |
| Multi-Agent AI Framework for Silicon-Validated Closed-Loop Design-Manufacturing Co-Optimization Chia-Yen Li, Yi-Chuen Eng, Chih-Wei Chiang, Zhe-Ju Liu, Jhong-Sheng Wang (Nexchip Semiconductor Corporation) | |
| 12:25 – 13:25 | Lunch Talk on SIGDA Vision 2030 |
| 13:25 – 14:25 | Session 6: Analog & RF Synthesis and Sizing |
| AnaFlow-RF: An Analog / RF Circuit Design Flow from Specification to Layout with Efficient Inference-Time LLM Reasoning-Guided RL Kaichang Chen, Mohsen Ahmadzadeh and Georges Gielen | |
| LASO-BOSS: LLM-driven Analog Sizing Optimization via Bayesian Optimization and Sizing Strategies Phuoc Pham, Arun Venkitaraman, Stefan Uhlich, Chia-Yu Hsieh, Andrea Bonetti, Markus Leibl, Simon Hofmann, Eisaku Ohbuchi, Lorenzo Servadei, Ulf Schlichtmann and Robert Wille | |
| G-DiffPS: Physics-Informed Graph Diffusion Policy for Amortized Multi-Topology RF Phase Shifter Synthesis Shadi Fall, Deepak Vungarala and Shaahin Angizi | |
| 14:25 – 14:45 | Coffee Break |
| 14:45 – 15:25 | Contest Session (4 talks × 10 min) |
| MLCAD 2026 Contest on Agentic Algorithm Discovery for Timing Optimization Atmadip Dey, Janakiraman Ethirajulu, Taizun Jafri, Vidya A. Chhabria | |
| Scientific Collaboration-Inspired Multi-Agent Algorithm Discovery for Post-Placement Optimization Kijung Kong, Dhoui Lim, Heechun Park | |
| MLCAD26 Contest Winner🏆: An Autonomous, Self-Evolving LLM Agent for Design-Adaptive QoR Optimization Taiyu Zhou, Jing Zhou, Jingyi Zhou | |
| TAPCO: LLM-Guided Design-Adaptive Timing and Power Co-Optimization Wuqian Tang, Zixiao Wang, Che-Chien Lin, Fong-Hua Fu, Laura Angélica Shion-Korsak, Xinyun Zhang, Bei Yu, Chun-Yao Wang | |
| 15:25 – 15:35 | Short Break |
| 15:35 – 16:20 | Poster Lightning Session (13 posters × 3 min) |
| Full-Chip Manhattan Mask Process Correction via Shared-Context Attention Graph Neural Networks Rui Xu, Haoxiang Jiang, Chuan Zhang, Jiaqi Liu, Junqi Yang and Chenxing Dong | |
| Differentiable Initialization-Accelerated CPU-GPU Hybrid Combinatorial Scheduling Mingju Liu, Jiaqi Yin, Alvaro Velasquez and Cunxi Yu | |
| HypCkt: A Hyperbolic Varitional Framework for Analog Circuit Topology Generation Yixin Chen, Haoning Jiang, Jiacheng Wang, Han Wu, Wei Zhang and Xiaopeng Yu | |
| Lithography Hotspot Detection via Dual-Scale Feature Contrast Enhancement Network Binling Luo, Ying Wang, Peng Gao, Yan Xing, Zihui Zhang, Xiaoming Xiong and Shuting Cai | |
| EXPLORE: Exploration with Guided Search for Analog Topology Generation using Language Models Guanglei Zhou, Chen-Chia Chang, Yikang Shen, Jonathan Ku, Isaac Jacobson, Jingyu Pan, Yiran Chen and Xin Zhang | |
| Reinforcement Learning Guided Boundary Activity Passing for Incremental Bounded Model Checking Sutirtha Bhattacharyya, Chandan Kumar Jha and Rolf Drechsler | |
| GNN-Based Cell Clustering for Placement Guidance in Designs with Half-Row-Extended Cells Ju-Hsuan Yu, Yu-Wei Chang, Wai-Kei Mak and Ting-Chi Wang | |
| HierRTLBench: Evaluating LLM-Based Verilog RTL Generation Under Context-Window Constraints Yashwant Rajesh, Karthikeya Patana, Durga Saranyu, Aathira Sunil, Sri Parameswaran, Kamesh Chandrasekar, Soumya Joshi and Paresh Saxena | |
| Little instead All: Full-Flow Matrix Inference for Multi-Corner Timing Acceleration Longze Wang, Yiyu Wang, Wei Xing and Yuanqing Cheng | |
| AnaCLARA: A Hierarchical Reasoning-Driven Constraint Generation Framework for Analog Layout Synthesis Kaichang Chen, Souradip Poddar, Georges Gielen and David Z. Pan | |
| From Tool Invocation to Source-Mechanism Exploration: Protected White-Box DSE for Open-Source EDA Zhiyu Zheng, Yiming Du, Ziyi Wang and Zhiang Wang | |
| VeriPQC: Efficient PQC Hardware Generation via Multi-Role Prompting and Formal Verification Asif Ronggon, Kimia Tasnia, Sazadur Rahman and Tasnuva Farheen | |
| GAPMA: Graph-Attention Cell Usage Prediction with Polarity-Minimized NPN Aggregation for Design-Specific Cell Composition Chung-Kuan Cheng, Junyeong Jang, Andrew B. Kahng, Byeonggon Kang and Jakang Lee | |
| 16:30 – 18:00 | Poster Session |
| 18:00 – 19:30 | Dinner |
✦ Wednesday, September 9, 2026 — Day 3
| 07:30 – 08:30 | Breakfast |
| 8:30 – 8:35 | Award Ceremony |
| 08:35 – 09:20 | Keynote 3: Automating Chip Design with Agentic AI Technology – From Chatbots to Long Running Agents Thomas Andersen (VP at Synopsys) |
| 09:20 – 09:30 | Short Break |
| 09:30 – 10:50 | Session 7: Physical Design & Manufacturability |
| Prompt-ETM: A Prompt-Tuned Spatio-Temporal Graph Framework for Cross-Node Electrothermal Migration Stress Prediction in 3D-IC PDNs Yunfan Zuo, Jiajun Shen, Kaixin Yang, Jiajie Xu, Chenpu Shi, Hao Yan and Longxing Shi | |
| SMUFTA: Simultaneous Multi-die Floorplanning and Technology Assignment Cristhian Roman-Vicharra, Prianka Sengupta, Runzhi Wang, Yiran Chen and Jiang Hu | |
| A Slicing-Free Polygon-Level Graph Learning Framework for Lithography Hotspot Detection Ranran Liu and Kun Ren | |
| X-Synth: A Fast Synthesis Framework for Cross-Scale Standard Cells via Pin-Access-Aware Multi-Task Routability Prediction Sehun Yu, Byungho Choi, Junbin Lee, Kijae Hong and Younggwang Jung | |
| 10:50 – 11:10 | Coffee Break |
| 11:10 – 12:30 | Session 8: Analog Design & Benchmarks |
| LOADBench: A Large Open Analog Dataset and Benchmark for Machine Learning in IC Design Markus Leibl, Filipe Azevedo, Stefan Uhlich, Andrea Bonetti, Arun Venkitaraman, Chia-Yu Hsieh, Phuoc Pham, Lorenzo Servadei, Helmut Graeb and Ricardo Martins | |
| NetGen: Failure-Aware Orchestrator Agents for Analog Netlist Generation Anish Mall, Dhruv Bhardwaj, Harsh Lakshakar and Ojas Pungalia | |
| Spicing up Genetic Netlist Generation with LLMs Stefan Uhlich, Yagiz Gencer, Andrea Bonetti, Arun Venkitaraman, Chia-Yu Hsieh, Eisaku Ohbuchi and Lorenzo Servadei | |
| NetlistBench: Evaluating LLM Reliability in SPICE Netlist Recognition and Manipulation Jiarui Ma, Jianghan Wang, Yuheng Ma, Ziyi Zhuang and Xiaoguang Liu | |
| 12:30 – 13:30 | Lunch |
| 13:30 – 14:30 | Session 9: Timing & Library Optimization |
| LIFT: A Physical-Aware Predictor for Fast Timing Evaluation in Custom-Cell DTCO Flows Chenpu Shi, Xinyao Chen, Yufan Chen, Jiajie Xu, Yunfan Zuo and Hao Yan | |
| MeTAL: ML-guided Technology Library Agonistic Logic Synthesis Akash Lal Dutta, Bhabesh Mali, Chandan Karfa, Sukanta Bhattacharjee and Arijit Hazra | |
| Efficient CCS Characterization for SRAM Macros Based on Anchor-Fused Waveform Reconstruction Aiganym Zhalinova, Jaeseung Baik, Sejun Park, Mingeun Song and Hanwool Jeong | |
| 14:30 – 14:50 | Coffee Break |
| 14:50 – 15:50 | Session 10: HLS & Design Space Exploration |
| Structure-augmented LLMs for High-Level Synthesis Pragma Optimization Haocheng Xu, Ye Qiao, Phyo Pyae Moe Aung, Alok Mishra, Pavana Prakash, Rolando Pablo Hong Enriquez, Adam Han Wu, Zhiheng Chen, Dejan Milojicic and Sitao Huang | |
| Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs Geetha Prasuna Yarramneni, Surya Selvam, Wilfried Haensch and Anand Raghunathan | |
| ResizerAgent: Agentic Strategy Selection for Timing Optimization in OpenROAD Resizer Vidya A. Chhabria, Atmadip Dey, Andrew B. Kahng, Ioannis Savidis, Pratik Shrestha and Bing-Yue Wu | |
| 15:50 – 16:00 | Closing Remarks |