The full program of the MLCAD Symposium 2024 will be available in August.
Accepted Papers
| ID | Title |
|---|---|
| 2 | Optimizing Predictive AI in Physical Design Flows with Mini Pixel Batch Gradient Descent |
| 6 | Efficient and Effective Neural Networks for Automatic Test Pattern Generation |
| 10 | Learning to Compare Hardware Designs for High-Level Synthesis |
| 11 | FACT: Fast and Accurate Multi-Corner Predictor for Timing Closure in Commercial EDA Flows |
| 12 | ICDaIR: Distribution-aware Static IR Drop Prediction Flow Based on Image Classification |
| 14 | Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning Strategies |
| 18 | An ML-aided Approach to Automatically Generate Schematic Symbols in PCB EDA Tools |
| 19 | IR-Aware ECO Timing Optimization Using Reinforcement Learning |
| 21 | ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis |
| 22 | A Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid Analysis |
| 23 | PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs |
| 28 | Flip-flop Centric Incremental Placement for Simultaneous Timing and Clock Network Power Optimization |
| 29 | Parallel Per-tile Activation with Linear Superposition of Thermal Response for Solving Arbitrary Power Pattern in 3DIC Thermal Simulation |
| 30 | Automated Physical Design Watermarking Leveraging Graph Neural Networks |
| 32 | Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis |
| 39 | Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models |
| 41 | High-Dimensional Yield Analysis Using Sparse Representation for Long-Tailed Distribution |
| 42 | An Efficient ML-based Hardware Trojan Localization Framework for RTL Security Analysis |
| 44 | AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design |
| 46 | LLM Based Physical Verification Runset Generator |
| 48 | TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path |
| 50 | Efficient Subgraph Matching Framework for Fast Subcircuit Identification |
| 51 | Utilizing Reinforcement Learning to Generate Adversarial Hardware Trojan Examples |
| 54 | OpenROAD-Assistant: An Open-Source Large Language Model for Physical Design Tasks |
| 55 | HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond |
| 57 | MinBLoG: Minimization of Boolean Logic Functions using Graph Attention Network |
| 65 | Thermal Map Dataset for Commercial Multi/Many Core CPU/GPU/TPU |
| 68 | Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design |
| 75 | Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning |
| 76 | Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization |
| 79 | LASP: LLM Assisted Security Property Generation for SoC Verification |
| 85 | ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging Effects |
| 87 | Enabling Risk Management of Machine Learning Predictions for FPGA Routability |
| 94 | Machine Learning VLSI CAD Experiments Should Consider Atomic Data Groups |
| 97 | Human Language to Analog Layout Using Glayout Layout Automation Framework |